The density of very large scale integration (VLSI) devices, incorporating complex functions operating at extreme circuit performances, has driven designers to integrate many diverse memory array macros within these devices. These memory macros range from large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories (CAMs), and many other special purpose functions. These highly integrated circuit functions in conjunction with state-of-the-art semiconductor technology advances usually result in relatively low device yields unless redundancy compensation is an integral part of the overall design. This is especially the case for array macros where the dense design of the memory cell has critical yield impacts.
Currently, VLSI devices incorporate structure to perform on-chip test functions. These built-in test and diagnostic functions are based on several Design for Test (DFT) techniques using scan chains testing techniques, such as Level Sensitive Scan Design (LSSD) and associated Logic & Array Built-in-self-test (LBIST & ABIST) devices, on-product-clock-generation (OPCG) techniques, and others. Many of the BIST designs are further based on Signature Analysis (SA) concepts as a response data compression method. As described by E. B. Eichelberger and T. W. Williams in an article entitled “A Logic Design Structure for LSI Testability” on pages 462-468 of the Proceedings of the 14th Design Automation Conf., LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD and built-in self test techniques include U.S. Pat. No. 3,783,254; No. 3,784,907; No. 3,961,252; No. 4,513,418; No. 6,181,614; No. 5,805,789; and No. 5,659,551. The subject matter of these patents and the above described Eichelberger and Williams article are hereby included by reference.
The problem addressed herein is encountered in the testing and determination of redundancy configurations for large numbers of small array macros in this ABIST and signature analysis design environment. Although the problem could be solved by a tedious and inefficient method of interactively testing each of the small arrays individually, this would result in excessive test time and complex test software support algorithms. Another approach may be to add logic support functions to each array to enable redundancy determination, but this would also result in the excessive chip real estate consumption overhead.